The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Jan. 08, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Aravinda Acharya, Bangalore, IN;

Wilson Pradeep, Karanataka, IN;

Prakash Narayanan, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01); G11C 29/56 (2006.01); G11C 29/12 (2006.01); G11C 29/20 (2006.01); G11C 29/32 (2006.01); G11C 29/50 (2006.01); G11C 29/14 (2006.01); G06F 11/26 (2006.01); G01R 31/14 (2006.01); G11C 29/10 (2006.01); G11C 29/36 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0757 (2013.01); G01R 31/31725 (2013.01); G01R 31/31858 (2013.01); G11C 29/12015 (2013.01); G11C 29/14 (2013.01); G11C 29/20 (2013.01); G11C 29/32 (2013.01); G11C 29/50012 (2013.01); G11C 29/56012 (2013.01); G01R 31/14 (2013.01); G06F 11/261 (2013.01); G11C 29/10 (2013.01); G11C 29/36 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/3202 (2013.01);
Abstract

A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.


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