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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11194383 B1

PDFFull Text
Date of Patent:
Dec. 07, 2021

Filed:

Sep. 13, 2016

Display device and method for controlling same

Applicant:

Casio Computer Co., Ltd., Tokyo, JP;

Inventor:

Kimiyasu Mizuno, Akishima, JP;

Assignee:

CASIO COMPUTER CO., LTD., Tokyo, JP;

Attorney:

Holtz, Holtz & Volek PC

Primary Examiner:

Julie Anne Watko

Int. Cl.
CPC ...
G06F 1/3293 (2019.01); G06F 1/3234 (2019.01); G06F 1/324 (2019.01); G09G 3/20 (2006.01); G09G 3/34 (2006.01); G06F 1/32 (2019.01); G06F 1/3212 (2019.01); G09G 3/36 (2006.01); G06F 3/14 (2006.01); G06F 1/3296 (2019.01); H04N 5/66 (2006.01); G06F 1/3218 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3293 (2013.01); G06F 1/32 (2013.01); G06F 1/3234 (2013.01); G06F 1/3265 (2013.01); G06F 1/3296 (2013.01); G06F 3/14 (2013.01); G06F 3/1446 (2013.01); G09G 3/20 (2013.01); G09G 3/34 (2013.01); G09G 3/3406 (2013.01); G09G 3/36 (2013.01); G06F 1/324 (2013.01); G09G 2300/023 (2013.01); G09G 2330/021 (2013.01); G09G 2330/022 (2013.01); G09G 2330/023 (2013.01); G09G 2330/027 (2013.01); G09G 2340/0435 (2013.01); H04N 5/66 (2013.01);
Abstract

A display device and a method for controlling same are provided which are capable of suppressing power consumption of an electronic apparatus while supplying a user with various types of information in various display formats. The display device has a first display block including a processor with relatively high processing power and a display section with high display performance and a second display block including a processor with relatively low processing power and a display section with low display performance. The processors mutually collaborate and are controlled to properly use the first display block and the second display block in accordance with an operation mode.

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