The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2021

Filed:

Dec. 04, 2018
Applicant:

Nec Corporation, Tokyo, JP;

Inventor:

Masaaki Tanio, Tokyo, JP;

Assignee:

NEC CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 3/00 (2006.01); H03K 5/01 (2006.01); H03K 19/21 (2006.01); H04B 1/04 (2006.01); H04B 1/16 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03M 3/436 (2013.01); H03K 5/01 (2013.01); H03K 19/21 (2013.01); H04B 1/04 (2013.01); H04B 1/16 (2013.01); H03K 2005/00078 (2013.01);
Abstract

A second-order ΔΣ modulator includes: a two-stage integrator; a first arithmetic operation circuit; and a second arithmetic operation circuit. The two-stage integrator includes a plurality of adder arrays, each of which includes a plurality of adders. The plurality of adder arrays includes first to fourth adder arrays. An output of a last stage of the second adder array is fed back as an input of a first stage of the first adder array. An output of a last stage of the fourth adder array is fed back as an input of a first stage of the third adder array. A sum bit string obtained in the first adder array is input to the third adder array. A sum bit string obtained in the second adder array is input to the fourth adder array.


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