The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2021

Filed:

Sep. 23, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

John Arnold, North Chatham, NY (US);

Dominik Metzler, Saratoga Springs, NY (US);

Ashim Dutta, Menands, NY (US);

Donald Canaperi, Bridgewater, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 43/02 (2006.01); H01L 27/22 (2006.01); H01L 43/12 (2006.01); H01L 43/10 (2006.01); H01L 43/08 (2006.01); H01L 41/27 (2013.01); H01L 41/22 (2013.01); H01L 43/04 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); G11C 11/161 (2013.01); H01L 27/222 (2013.01); H01L 41/22 (2013.01); H01L 41/27 (2013.01); H01L 43/04 (2013.01); H01L 43/08 (2013.01); H01L 43/10 (2013.01); H01L 43/12 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/16 (2013.01);
Abstract

Methods for forming an integrated circuit are provided. Aspects include providing a wafer substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure, the memory area interconnect structure comprising metal interconnects formed within a first interlayer dielectric, recessing a portion of the memory area interconnect structure, forming a bottom electrode contact on the recessed portion of the memory area interconnect structure, forming a bottom electrode over the bottom electrode contact, forming a protective dielectric layer over the non-memory area interconnect structure, and forming memory element stack layers on a portion of the bottom electrode.


Find Patent Forward Citations

Loading…