The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2021

Filed:

Jan. 10, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seung Soo Hong, Suwon-si, KR;

Jeong Yun Lee, Suwon-si, KR;

Geum Jung Seong, Suwon-si, KR;

Jin Won Lee, Suwon-si, KR;

Hyun Ho Jung, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 27/02 (2006.01); H01L 21/8234 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 27/0207 (2013.01); H01L 27/1104 (2013.01); H01L 29/66545 (2013.01);
Abstract

A semiconductor device including a plurality of active regions extending in a first direction on a substrate; a device isolation layer between the plurality of active regions such that upper portions of the plurality of active regions protrude from the device isolation layer; a first gate electrode and a second gate electrode extending in a second direction crossing the first direction and intersecting the plurality of active regions, respectively, on the substrate, the first gate electrode being spaced apart from the second gate electrode in the second direction; a first gate separation layer between the first gate electrode and the second gate electrode; and a second gate separation layer under the first gate separation layer and between the first gate electrode and the second gate electrode, the second gate separation layer extending into the device isolation layer in a third direction crossing the first direction and the second direction.


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