The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2021

Filed:

Oct. 01, 2020
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Shigehiro Asano, Yokosuka Kanagawa, JP;

Neil Buxton, Caversham, GB;

Julien Margetts, Thame, GB;

Shunichi Igahara, Kamakura Kanagawa, JP;

Takehiko Amaki, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/34 (2006.01); G11C 8/12 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3431 (2013.01); G11C 8/12 (2013.01); G11C 16/26 (2013.01); G11C 16/3495 (2013.01); G11C 16/0483 (2013.01);
Abstract

A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.


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