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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11188697 B1

PDFFull Text
Date of Patent:
Nov. 30, 2021

Filed:

Jan. 05, 2021

On-chip memory access pattern detection for power and resource reduction

Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Chaithanya Dudha, San Jose, CA (US);

Rajeev Patwari, Campbell, CA (US);

Nithin Kumar Guggilla, Hyderabad, IN;

Ashish Sirasao, San Jose, CA (US);

Krishna Garlapati, Los Gatos, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:

Kevin T. Cuenot

Primary Examiner:

Phallaka Kik

Int. Cl.
CPC ...
G06F 30/333 (2020.01); G06F 30/343 (2020.01); G06F 30/3308 (2020.01); G06F 30/398 (2020.01); G06F 11/00 (2006.01); G06F 9/34 (2018.01); G06F 9/26 (2006.01); G06F 13/00 (2006.01); G01R 31/28 (2006.01); G11C 7/10 (2006.01); G11C 29/04 (2006.01); G11B 27/36 (2006.01); G11B 7/00 (2006.01); G11B 11/00 (2006.01); H01L 21/00 (2006.01); G06F 11/32 (2006.01); G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
G06F 30/333 (2020.01); G06F 11/324 (2013.01); G06F 30/3308 (2020.01); G06F 30/343 (2020.01); G11C 7/10 (2013.01); G01R 31/28 (2013.01); G06F 9/26 (2013.01); G06F 9/34 (2013.01); G06F 12/00 (2013.01); G06F 13/00 (2013.01); G06F 30/398 (2020.01); G11B 7/00 (2013.01); G11B 11/00 (2013.01); G11B 27/36 (2013.01); G11C 29/04 (2013.01); H01L 21/00 (2013.01);
Abstract

Determining on-chip memory access patterns can include modifying a circuit design to include a profiler circuit for a random-access memory (RAM) of the circuit design, wherein the profiler circuit is configured to monitor an address bus of the RAM, and modifying the circuit design to include a debug circuit connected to the profiler circuit. Usage data for the RAM can be generated by detecting, using the profiler circuit, addresses of the RAM accessed during a test of the circuit design, as implemented in an integrated circuit. The usage data for the RAM can be output using the debug circuit.

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