The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2021
Filed:
May. 23, 2019
Xilinx, Inc., San Jose, CA (US);
Akella Sastry, San Jose, CA (US);
Vinod K. Kathail, Palo Alto, CA (US);
L. James Hwang, Portola Valley, CA (US);
Shail Aditya Gupta, San Jose, CA (US);
Vidhumouli Hunsigida, Hyderabad, IN;
Siddharth Rele, Navi Mumbai, IN;
Xilinx, Inc., San Jose, CA (US);
Abstract
For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.