Pixel charge control circuit in digital devices for images acquisition

Abstract

A digital device for image acquisition () comprises at least one selection decoder circuit () and a plurality of sub-blocks () each comprising one or more pixels () and a corresponding charge control circuit () which provides a circuit suitable for realizing a logic port of the AND type () having a selector input terminal () which receives the selection signal from the selection decoder circuit () and a suitable enabling input terminal () to receive an enabling signal; and interruption organs () connected to the reset terminal () of the pixel () to transmit a reset signal constituted alternatively by a signal output from the aforesaid circuit suitable for realizing a logic port of the AND type () or from a global reset signal transmitted to a corresponding global reset terminal (). The reset signal of a sub-block can be controlled directly by the selection decoder (), while the global signal transmitted to the global reset terminal () may be a digital signal suitable for performing a global reset of all the pixels of the device; it can be an analog global signal of the type suitable to limit the blooming effect or to obtain high dynamics.