The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 2021
Filed:
Jul. 27, 2020
Applicant:
Stmicroelectronics (Rousset) Sas, Rousset, FR;
Inventors:
Franck Julien, La Penne sur Huveaune, FR;
Abderrezak Marzaki, Aix en Provence, FR;
Assignee:
STMicroelectronics (Rousset) SAS, Rousset, FR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11531 (2017.01); H01L 27/11543 (2017.01); H01L 27/11546 (2017.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/311 (2006.01); H01L 27/11521 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11531 (2013.01); H01L 21/02164 (2013.01); H01L 21/26513 (2013.01); H01L 21/31111 (2013.01); H01L 27/11521 (2013.01); H01L 29/40114 (2019.08); H01L 29/66537 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract
A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.