The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2021

Filed:

Nov. 11, 2019
Applicant:

Ultramemory Inc., Tokyo, JP;

Inventors:

Fumitake Okutsu, Tokyo, JP;

Takao Adachi, Tokyo, JP;

Assignee:

ULTRAMEMORY INC., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 25/50 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/92242 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06551 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/1434 (2013.01);
Abstract

The present invention is intended to provide a semiconductor module and a DIMM module that are capable of stably supplying power to a plurality of stacked memory chips, a manufacturing method of the semiconductor module and a manufacturing method of the DIMM module. The semiconductor modulehaving a plurality of memory chipsincludes: a memory substratehaving a power supply circuitexposed on an arrangement surface as one surface of the memory substrate; and at least one memory unitarranged over the arrangement surface of the memory substrate. The memory unitincludes: the plurality of memory chipsstacked together such that a stacking direction D is along the arrangement surface; a through electrodepassing through the plurality of memory chipsin the stacking direction D; and an electrode layerformed on one end surface in the stacking direction D and connected to the through electrodeand the power supply circuit


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