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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11182526 B1

PDFFull Text
Date of Patent:
Nov. 23, 2021

Filed:

Sep. 25, 2019

Methods for engineering integrated circuit design and development

Applicant:

Efabless Corporation, San Jose, CA (US);

Inventors:

Bertrand Irissou, San Jose, CA (US);

John M. Hughes, Hartford, CT (US);

Lucio Lanza, Palo Alto, CA (US);

Mohamed K. Kassem, Carlsbad, CA (US);

Michael S. Wishart, Hillsborough, CA (US);

Rajeev Srivastava, Austin, TX (US);

Risto Bell, San Jose, CA (US);

Robert Timothy Edwards, Poolesville, MD (US);

Sherif Eid, Sunnyvale, CA (US);

Greg P. Shaurette, Tahoe City, CA (US);

Assignee:

efabless corporation, San Jose, CA (US);

Attorney:

Penilla IP, APC

Primary Examiner:

Phallaka Kik

Int. Cl.
CPC ...
G06F 30/39 (2020.01); G06F 30/30 (2020.01); G06F 30/33 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/3323 (2020.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G06F 30/39 (2020.01); G06F 30/30 (2020.01); G06F 30/33 (2020.01); G06F 30/3323 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); H01L 23/573 (2013.01);
Abstract

Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.

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