The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 2021
Filed:
Aug. 21, 2019
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Ahmad R. Ansari, San Jose, CA (US);
Sagheer Ahmad, Cupertino, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); H03K 19/17728 (2020.01); G11C 5/14 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G06F 5/06 (2006.01); G06F 13/16 (2006.01); G06F 1/3206 (2019.01); G11C 7/24 (2006.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0683 (2013.01); G06F 1/3206 (2013.01); G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 5/06 (2013.01); G06F 13/16 (2013.01); G11C 5/14 (2013.01); G11C 5/148 (2013.01); G11C 7/222 (2013.01); G11C 7/225 (2013.01); G11C 7/24 (2013.01); G11C 11/4076 (2013.01); H03K 19/17728 (2013.01); H03K 19/1738 (2013.01);
Abstract
A memory block circuit can include a plurality of data interfaces, a switch connected to each data interface of the plurality of data interfaces, and a plurality of memory banks each coupled to the switch. Each memory bank can include a memory controller and a random access memory connected to the memory controller. The memory block circuit also includes a control interface and a management controller connected to the control interface and each memory bank of the plurality of memory banks. Each memory bank can be independently controlled by the management controller.