The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2021

Filed:

Sep. 25, 2020
Applicant:

Honeywell International Inc., Charlotte, NC (US);

Inventors:

David C. Vacanti, Renton, WA (US);

Marc M. Pos, Duvall, WA (US);

Assignee:

Honeywell International Inc., Charlotte, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01S 7/41 (2006.01); G01S 13/93 (2020.01); G01S 7/35 (2006.01); G01S 7/292 (2006.01); G01S 7/282 (2006.01); H03L 7/099 (2006.01); H03L 7/22 (2006.01); G01S 7/03 (2006.01); G01S 13/91 (2006.01);
U.S. Cl.
CPC ...
G01S 7/41 (2013.01); G01S 7/032 (2013.01); G01S 7/282 (2013.01); G01S 7/292 (2013.01); G01S 7/35 (2013.01); G01S 7/354 (2013.01); G01S 13/93 (2013.01); H03L 7/0991 (2013.01); H03L 7/22 (2013.01); G01S 13/91 (2013.01);
Abstract

In some examples, a radar system includes first direct digital synthesizer (DDS) circuitry and first phase-locked loop (PLL) circuitry configured to generate a first sinusoidal signal based on a first DDS signal generated by the first DDS circuitry. In some examples, the radar system further includes transmitter circuitry configured to generate a radar signal based on the first sinusoidal signal. In some examples, the radar system also includes one or more antennas configured to transmit the radar signal and receive a return signal based on the radar signal. In some examples, the radar system includes second DDS circuitry, second PLL circuitry configured to generate a second sinusoidal signal based on a second DDS signal generated by the second DDS circuitry, and receiver circuitry configured to process the return signal based on the second sinusoidal signal.


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