The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Jul. 28, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Baleegh Abdo, Fishkill, NY (US);

Nicholas T. Bronn, Long Island City, NY (US);

Oblesh Jinka, Stamford, CT (US);

Salvatore B. Olivadese, Stamford, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); G06N 99/00 (2019.01); G01R 33/02 (2006.01); H01L 23/04 (2006.01); H01L 23/22 (2006.01); H01L 23/24 (2006.01); G06N 10/00 (2019.01); H01L 39/04 (2006.01); H05K 1/02 (2006.01); H03D 7/00 (2006.01); H03F 19/00 (2006.01); H05K 1/11 (2006.01); H05K 3/30 (2006.01); H05K 3/40 (2006.01); H05K 3/46 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/183 (2013.01); G06N 10/00 (2019.01); H01L 39/045 (2013.01); H03D 7/005 (2013.01); H03F 19/00 (2013.01); H05K 1/0243 (2013.01); H05K 1/0298 (2013.01); H05K 1/115 (2013.01); H05K 1/185 (2013.01); H05K 3/30 (2013.01); H05K 3/4038 (2013.01); H05K 1/0216 (2013.01); H05K 3/0011 (2013.01); H05K 3/4697 (2013.01); H05K 2201/1056 (2013.01); H05K 2201/10371 (2013.01);
Abstract

An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.


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