The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Aug. 14, 2020
Applicant:

Osram Oled Gmbh, Regensburg, DE;

Inventors:

Tony Albrecht, Bad Abbach, DE;

Tamas Lamfalusi, Regensburg, DE;

Christian Gatzhammer, Lupburg, DE;

Assignee:

OSRAM OLED GmbH, Regensburg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/54 (2010.01); H01L 33/50 (2010.01); H01L 33/56 (2010.01); H01L 33/48 (2010.01);
U.S. Cl.
CPC ...
H01L 33/54 (2013.01); H01L 33/0093 (2020.05); H01L 33/486 (2013.01); H01L 33/502 (2013.01); H01L 33/56 (2013.01); H01L 33/50 (2013.01); H01L 2933/005 (2013.01); H01L 2933/0041 (2013.01);
Abstract

An optoelectronic component includes an optoelectronic semiconductor chip including a connection surface; a first potting body; and a second potting body, wherein the first potting body covers all lateral side surfaces and the top surface of the semiconductor chip, the first potting body has a bottom surface flush with the connection surface, the second potting body has a bottom surface flush with the bottom surface, the second potting body completely covers all side surfaces of the first potting body facing away from the semiconductor chip, a top surface of the second potting body on the opposite of the connection surface is convexly curved, the first and second potting bodies have a contour in a lateral plane that is not similar, and the optoelectronic semiconductor chip has exclusively on its connection surface exposed electrical contact surfaces via which the semiconductor chip is electrically connectable and operable.


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