The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

May. 18, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jung-In Kim, Seoul, KR;

Youngnam Hwang, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 11/4096 (2006.01); G11C 11/4097 (2006.01); G11C 11/408 (2006.01); G11C 11/4074 (2006.01); G11C 11/4091 (2006.01); G11C 14/00 (2006.01); G11C 11/54 (2006.01); G06N 3/063 (2006.01); G11C 13/00 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G06N 3/063 (2013.01); G06N 3/0635 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4097 (2013.01); G11C 11/54 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 14/009 (2013.01); G11C 11/5664 (2013.01); H01L 45/122 (2013.01);
Abstract

A neuromorphic processor may include at least a first synapse element. The first synapse element may include a first bit cell and a second bit cell, the first bit cell connected to a first bitline, a first inverted bitline, a first wordline, and a first inverted wordline, and the second bit cell connected to the first bitline, the first inverted bitline, a second wordline, and a second inverted wordline. The first synapse element may be configured to receive a first input through the first wordline, the first inverted wordline, the second wordline, and the second inverted wordline, store a first synapse value in the first bit cell and the second bit cell, perform a calculation operation using the first input and the first synapse value, and output a result of the calculation through the first bitline and the first inverted bitline.


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