The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Feb. 26, 2021
Applicant:

Edgecortix Pte. Ltd., Singapore, SG;

Inventors:

Nikolay Nez, Tokyo, JP;

Antonio Tomas Nevado Vilchez, Tokyo, JP;

Hamid Reza Zohouri, Sunnyvale, CA (US);

Mikhail Volkov, Tokyo, JP;

Oleg Khavin, Tokyo, JP;

Sakyasingha Dasgupta, Tokyo, JP;

Assignee:

EDGECORTIX PTE. LTD., Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2006.01); G06N 3/10 (2006.01); G06N 3/04 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06N 3/04 (2013.01); G06N 3/10 (2013.01);
Abstract

Neural network accelerator hardware-specific division of inference may be performed by operations including obtaining a computational graph and a hardware chip configuration. The operations also include dividing inference of the plurality of layers into a plurality of groups. Each group includes a number of sequential layers based on an estimate of duration and energy consumption by the hardware chip to perform inference of the neural network by performing the mathematical operations on activation data, sequentially by layer, of corresponding portions of layers of each group. The operations further include generating instructions for the hardware chip to perform inference of the neural network, sequentially by group, of the plurality of groups.


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