The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Aug. 31, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Pradip Jha, Cupertino, CA (US);

Brendan Matthew O'Higgins, Sunnyvale, CA (US);

Dinesh K. Monga, Santa Clara, CA (US);

Bart Reynolds, Manzanita, OR (US);

Ryan Linderman, Longmont, CO (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/327 (2020.01); G06F 30/33 (2020.01); G06F 9/451 (2018.01); G06F 15/78 (2006.01); G06F 30/39 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 9/451 (2018.02); G06F 15/7825 (2013.01); G06F 30/33 (2020.01); G06F 30/39 (2020.01);
Abstract

A unified data model for creating a circuit design for a heterogeneous integrated circuit is provided. The unified data model is stored as a data structure in computer hardware. The unified data model includes a unified netlist specifying the circuit design and a unified device model representing the heterogeneous integrated circuit. The unified netlist includes netlist objects configured to communicate over bitwise connections and network connections representing packet-based communications. The unified netlist may be mapped to the unified device model using computer hardware. Using the computer hardware, at least a portion of the device model may be displayed in coordination with at least a portion of the unified netlist mapped thereto.


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