The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Nov. 01, 2019
Applicant:

Emc Ip Holding Company Llc, Hopkinton, MA (US);

Inventor:

James Guyer, Northboro, MA (US);

Assignee:

EMC IP Holding Company LLC, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/20 (2006.01); G06F 12/14 (2006.01); G06F 12/0831 (2016.01); G06F 12/06 (2006.01); G06F 12/02 (2006.01); G06F 12/0806 (2016.01);
U.S. Cl.
CPC ...
G06F 13/1652 (2013.01); G06F 12/0284 (2013.01); G06F 12/0292 (2013.01); G06F 12/063 (2013.01); G06F 12/0806 (2013.01); G06F 12/0835 (2013.01); G06F 12/1441 (2013.01); G06F 13/20 (2013.01); G06F 2212/62 (2013.01);
Abstract

A system may include a plurality processing cores for processing I/O operations and at least one interconnect component for communicatively coupling one or more external components to the plurality of processing cores. The at least one interconnect component may be directly physically connected to each of the plurality of processing cores. The interconnect component may route I/O operations to one of the processing cores based on a memory range of the I/O operation. An I/O communication including an I/O operation may be received at the interconnect component. The memory address range of the I/O operation may be determined. A processing core corresponding to the determined memory address range of the I/O operation may be determined, for example, by accessing a data structure that maps address ranges to processing cores. An I/O communication including the I/O operation may be sent from the interconnect component to the determined processing core.


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