The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Mar. 13, 2020
Applicant:

Shenzhen Goodix Technology Co., Ltd., Shenzhen, CN;

Inventors:

Bassam S. Kamand, San Diego, CA (US);

Waleed Younis, San Diego, CA (US);

Ramon Zuniga, San Diego, CA (US);

Jagadish Rongali, San Diego, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0895 (2016.01); G06F 12/084 (2016.01); G06F 9/30 (2018.01); G06F 13/16 (2006.01); G06F 12/0853 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0895 (2013.01); G06F 9/30087 (2013.01); G06F 12/084 (2013.01); G06F 12/0853 (2013.01); G06F 13/1689 (2013.01);
Abstract

A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.


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