The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 2021
Filed:
Feb. 13, 2017
International Business Machines Corporation, Armonk, NY (US);
Gregory W. Alexander, Pflugerville, TX (US);
James J. Bonanno, Wappingers Falls, NY (US);
Adam B. Collura, Hopewell Junction, NY (US);
Bruce C. Giamei, Lagrangeville, NY (US);
Christian Jacobi, West Park, NY (US);
Jang-Soo Lee, Poughkeepsie, NY (US);
Edward T. Malley, New Rochelle, NY (US);
Lawrence J. Powell, Jr., Round Rock, TX (US);
Anthony Saporito, Highland, NY (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
A computer-implemented method for marking load and store instruction overlap in a processor pipeline is described. The method includes detecting a load instruction following a store instruction in an instruction stream. The load instruction and the store instruction include instruction text. The instruction text includes operand address information. The method includes comparing operand address information of the store instruction with operand address information of the load instruction to determine whether there is a memory image overlap in an issue queue between the operand address information of the store instruction and the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to determining that there is a memory image overlap.