The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Oct. 02, 2018
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, JP;

Inventors:

Yuichiro Horiguchi, Chiyoda-ku, JP;

Satoshi Nishikawa, Chiyoda-ku, JP;

Koichi Akiyama, Chiyoda-ku, JP;

Keigo Fukunaga, Chiyoda-ku, JP;

Yohei Hokama, Chiyoda-ku, JP;

Yosuke Suzuki, Chiyoda-ku, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/035 (2006.01); G02F 1/025 (2006.01); B29D 11/00 (2006.01);
U.S. Cl.
CPC ...
G02F 1/025 (2013.01); B29D 11/00673 (2013.01);
Abstract

An optical semiconductor device includes a semiconductor substrate, a first semiconductor layer provided on the semiconductor substrate, and a mesa waveguide provided on the principal surface of the first semiconductor layer. The semiconductor device also includes a buried layer covering the upper surface of the first semiconductor layer. Part of the upper surface of the first semiconductor layer is exposed. A mesa structure provided at the boundary between a part of the first semiconductor layer is covered with the buried layer and a part of the first semiconductor layer is exposed. One side of the mesa structure is covered with the buried layer, and the other side is exposed. The optical semiconductor device can reduce the generation of stress in the buried layer, for example, to suppress the occurrence of cracks in the buried layer and enhance the reliability.


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