The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Feb. 15, 2021
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Neha Srivastava, New Delhi, IN;

Shreya Singh, Ranchi, IN;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 31/3177 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/31724 (2013.01);
Abstract

A system-on-chip (SoC) is disclosed. The SoC includes a set of fake fault injection circuits and a critical intellectual property (IP) core that includes first and second control circuits. The first and second control circuits are each operable in a test mode and a functional mode. The first and second control circuits are operated in the functional mode in lockstep in an absence of a fake fault input. In a presence of the fake fault input, one of the first and second control circuits is switched from the functional mode to the test mode. One of the first and second control circuits operating the test mode generates a fake fault response for the fake fault input. The critical IP core is determined as one of error-free and erroneous based on a detection of the generated fake fault response as one of error-free and erroneous, respectively.


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