The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Feb. 07, 2019
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventor:

Shinya Nakano, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 17/00 (2006.01); G11C 11/413 (2006.01); G11C 29/38 (2006.01); H04N 5/3745 (2011.01); H04N 5/378 (2011.01); G11C 7/22 (2006.01); G11C 11/419 (2006.01); G11C 8/04 (2006.01); B60Q 9/00 (2006.01); B60R 1/00 (2006.01);
U.S. Cl.
CPC ...
H04N 17/002 (2013.01); G11C 7/22 (2013.01); G11C 8/04 (2013.01); G11C 11/413 (2013.01); G11C 11/419 (2013.01); G11C 29/38 (2013.01); H04N 5/378 (2013.01); H04N 5/37452 (2013.01); B60Q 9/00 (2013.01); B60R 1/00 (2013.01); B60R 2300/105 (2013.01); B60R 2300/30 (2013.01); G11C 2207/2209 (2013.01);
Abstract

An imaging device includes a first memory configured to perform writing to multiple addresses thereof by designating the multiple addresses on address-by-address basis, a second memory configured to perform writing simultaneously to multiple address thereof, and a control circuit that controls readout of signals from the first memory and the second memory. The control circuit is configured to perform a first operation mode to sequentially designate the multiple addresses of the first memory and sequentially perform readout of signals from the multiple addresses of the first memory, and a second operation mode to sequentially designate the multiple addresses of the second memory and sequentially perform readout of signals from the multiple addresses of the second memory so that an output value from the second memory becomes the same as a value expected as an output value from the first memory in the first operation mode.


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