Digital equalizer with overlappable filter taps

Abstract

In one illustrative embodiment, an equalizer includes: a shift register, an array of multipliers, an array of multiplexers, and a summer. The shift register provides receive signal samples at each tap. Each multiplier in the array multiplies one of said receive signal samples by a respective coefficient to produce a product, with at least one of said multipliers coupled to a fixed tap. Each multiplexer in the array supplies an associated one of said multipliers with a receive signal sample from a selectable tap. The summer sums the products to produce a filtered output signal. To reduce hardware requirements, coefficient multipliers may be multiplexed to a reduced set of taps, and the dynamic range of the coefficients may be increased by overlapping the sets for different multipliers. Methods of tap selection and coefficient adaptation are disclosed.