The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2021
Filed:
Jun. 24, 2020
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Sung Eun Lee, Icheon-si, KR;
Young Ook Song, Seoul, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/29 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
H03M 13/2906 (2013.01); G06F 11/1076 (2013.01); H03M 13/616 (2013.01);
Abstract
A parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity in a first error correction mode having a first error correction capability for original data. The second parity generation part is configured to generate a second parity using the first parity in a second error correction mode having a second error correction capability.
Lee, Sung. (2021). Parity generation circuits for a plurality of error correction levels, memory controllers, and memory modules including the parity generation circuits (U.S. Patent No. 11171670). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11171670
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile