The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Dec. 04, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:
Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02P 8/12 (2006.01); G01R 19/165 (2006.01); H03K 5/24 (2006.01); H03M 1/00 (2006.01); H02P 7/03 (2016.01); H02P 8/22 (2006.01); H03K 17/687 (2006.01); H03K 3/3565 (2006.01);
U.S. Cl.
CPC ...
H02P 8/12 (2013.01); G01R 19/16519 (2013.01); H02P 7/04 (2016.02); H02P 8/22 (2013.01); H03K 3/3565 (2013.01); H03K 5/24 (2013.01); H03K 17/687 (2013.01); H03K 17/6871 (2013.01); H03M 1/001 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01);
Abstract

An integrated circuit includes an H-bridge circuit having a first output node for coupling to a high-side terminal of an inductor and a second output node for coupling to a low-side terminal of the inductor. A current sense FET is coupled between a current source and the lower supply voltage to provide a reference current that includes a peak current limit at a sensing node. A current-sense comparator has a first input coupled to the sensing node, a second input coupled to the second output node and an output coupled to send an output signal towards a driver control circuit. A FET linear detection circuit is coupled to receive a gate voltage of an active low-side power FET and has an output coupled to enable the current-sense comparator when the active low-side power FET is operating in a linear region.


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