The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Dec. 28, 2017
Applicant:

3-5 Power Electronics Gmbh, Dresden, DE;

Inventor:

Volker Dudek, Ettlingen, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/36 (2006.01); H01L 29/20 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/207 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7395 (2013.01); H01L 29/0696 (2013.01); H01L 29/105 (2013.01); H01L 29/20 (2013.01); H01L 29/207 (2013.01); H01L 29/36 (2013.01); H01L 29/7397 (2013.01); H01L 29/7396 (2013.01);
Abstract

IGBT semiconductor structure having a psubstrate, an nlayer, at least one p region adjacent to the nlayer, and at least one nregion adjacent to the p region, a dielectric layer and three terminal contacts. The p region forms a first p-n junction together with the nlayer, and the nregion forms a second p-n junction together with the at least one p region. The dielectric layer covers the first p-n junction and the second p-n junction. The second terminal contact is implemented as a field plate on the dielectric layer and a doped intermediate layer with a layer thickness of 1 μm-50 μm and a dopant concentration of 10-10cmis arranged between the psubstrate and the nlayer, wherein the intermediate layer is integrally joined to at least the psubstrate.


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