The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Jun. 12, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hong-Hyun Park, Fremont, CA (US);

Zhengping Jiang, San Jose, CA (US);

Hesameddin Ilatikhameneh, Sunnyvale, CA (US);

Woosung Choi, Milpitas, CA (US);

Chihak Ahn, Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 29/04 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1033 (2013.01); H01L 21/0259 (2013.01); H01L 21/0262 (2013.01); H01L 21/02609 (2013.01); H01L 29/045 (2013.01); H01L 29/0847 (2013.01); H01L 29/66522 (2013.01); H01L 29/66568 (2013.01);
Abstract

A method of manufacturing a p-type MOSFET includes depositing a channel material to form a channel region, forming a source region and a drain region on each side of the channel region along a first direction, depositing a gate oxide layer on the channel region along a second direction crossing the first direction, and depositing a gate electrode on the gate oxide. The channel material includes a group IV element or III-V semiconductor compound and have a diamond or zincblende cubic crystal structure. A <001> direction of the crystal structure is parallel to the second direction. Two adjacent atoms on an out-most atomic layer of the channel region along the first direction are connected to each other via a single intervening atom, and an interface between the gate oxide layer and the channel region has a surface roughness of 1 angstrom or lower.


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