The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Mar. 07, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Takashi Yuda, Yokkaichi, JP;

Hiroyuki Kamiya, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 27/11565 (2017.01); H01L 27/11573 (2017.01); H01L 21/306 (2006.01); H01L 23/522 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 27/11556 (2017.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01); H01L 27/11526 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0262 (2013.01); H01L 21/30608 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 29/40117 (2019.08); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating sack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a pedestal channel portion, a memory film overlying the pedestal channel portion, a vertical semiconductor channel located inside the memory film, and a channel connection strap that extends through an opening of the memory film and contacting the pedestal channel portion and the vertical semiconductor channel. The channel connection strap has a topmost surface located below a horizontal plane including a top surface of the vertical semiconductor channel. The channel connection strap portion may be formed by a selective semiconductor growth from physically exposed semiconductor surfaces, and may provide enhanced electrical connection between the pedestal channel portion and the vertical semiconductor channel.


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