The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Feb. 26, 2020
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Yuichiro Hinata, Matsumoto, JP;

Tatsuo Nishizawa, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/49 (2006.01); H01L 23/498 (2006.01); H01L 25/18 (2006.01); H01L 21/48 (2006.01); H01L 25/07 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 21/4853 (2013.01); H01L 23/49833 (2013.01); H01L 25/072 (2013.01); H01L 25/18 (2013.01); H01L 23/3107 (2013.01);
Abstract

A semiconductor device includes an insulated circuit board having conductor layers arranged away from each other and bonding materials each provided on the conductor layers; a wiring board having an opposing surface facing the conductor layers and through holes each corresponding to a position of each bonding material; hollow members each having a cylindrical portion and a flanged portion at one end of the cylindrical portion and having a cavity in common with the cylindrical portion, ok cylindrical portions press-fitted into the through holes, and other ends of the cylindrical portions bonded to the conductor layers by the bonding materials; and external connection terminals each inserted into the cavity of each hollow member and bonded to the conductor layers. Each cylindrical portion is inserted into each through hole such that each flanged portion contacts with an upper surface opposed to the opposing surface of the wiring board.


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