The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Aug. 15, 2019
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventors:

Maiko Hatano, Kyoto, JP;

Takukazu Otsuka, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 21/52 (2006.01); H01L 23/12 (2006.01); H01L 23/373 (2006.01); H01L 23/00 (2006.01); H01L 29/12 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 21/52 (2013.01); H01L 23/12 (2013.01); H01L 23/3735 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 29/12 (2013.01); H01L 29/739 (2013.01); H01L 29/78 (2013.01); H05K 3/341 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01);
Abstract

A power module includes: a plate-shaped thick copper substrate, a conductive stress relaxation metal layer disposed on the thick copper substrate, a semiconductor device disposed on the stress relaxation metal layer, and a plated layer disposed on the stress relaxation metal layer, wherein the semiconductor device is bonded to the stress relaxation metal layer via the plated layer. The thick copper substrate includes a first thick copper layer and a second thick copper layer disposed on the first thick copper layer, and the stress relaxation metal layer is disposed on the second thick copper layer. A part of the semiconductor device is embedded to be fixed to the stress relaxation metal layer. A bonded surface between the semiconductor device and the stress relaxation metal layer are integrated to each other by means of diffusion bonding or solid phase diffusion bonding.


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