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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11170855 B1

PDFFull Text
Date of Patent:
Nov. 09, 2021

Filed:

Sep. 01, 2020

Semiconductor device and manufacturing method of the same

Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Yuka Itano, Yokkaichi Mie, JP;

Minoru Oda, Yokkaichi Mie, JP;

Masato Shini, Mie Mie, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:

Foley & Lardner LLP

Primary Examiner:

Tan T Nguyen

Int. Cl.
CPC ...
G11C 16/08 (2006.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); H01L 27/11526 (2017.01); H01L 27/11565 (2017.01); H01L 27/11553 (2017.01); H01L 27/1158 (2017.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 27/1158 (2013.01); H01L 27/11526 (2013.01); H01L 27/11553 (2013.01); H01L 27/11565 (2013.01);
Abstract

A semiconductor device according to an embodiment includes first and second chips, and a first conductor. The first chip includes a first substrate, a first circuit and a first joint metal. The first circuit is provided on the first substrate. The first joint metal is connected to the first circuit. The second chip includes a second substrate, a second circuit, and a second joint metal. The second substrate includes P-type and N-type well regions. The second circuit is provided on the second substrate and includes a first transistor. The second joint metal is connected to the second circuit and the first joint metal. The first conductor is connected to the N-type well region from a top region of the second chip. The P-type well region is arranged between a gate electrode of the first transistor and the N-type well region.

Find Patent Forward Citations

Itano, Yuka. (2021). Semiconductor device and manufacturing method of the same (U.S. Patent No. 11170855). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11170855

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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