The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Jul. 17, 2020
Applicant:

Mentium Technologies Inc., Santa Barbara, CA (US);

Inventors:

Farnood Merrikh Bayat, Santa Barbara, CA (US);

Jaroslaw Sulima, Santa Barbara, CA (US);

Mirko Prezioso, Santa Barbara, CA (US);

Assignee:

MENTIUM TECHNOLOGIES INC., Santa Barbara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/406 (2006.01); G11C 11/4074 (2006.01); G11C 5/02 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01); G01R 19/00 (2006.01); G01R 19/10 (2006.01); G05F 1/56 (2006.01); G05F 1/575 (2006.01); G11C 7/10 (2006.01); G11C 11/4094 (2006.01); G11C 11/4097 (2006.01); H03K 17/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40626 (2013.01); G01R 19/0038 (2013.01); G01R 19/10 (2013.01); G05F 1/561 (2013.01); G05F 1/575 (2013.01); G11C 5/025 (2013.01); G11C 7/1096 (2013.01); G11C 11/4074 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01); G11C 11/4097 (2013.01); H03K 17/22 (2013.01);
Abstract

A memory system having a temperature effect compensation mechanism is provided. The memory system may include a plurality of memory cells, where the memory cells are organized in an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically. The plurality of memory cells may have an operating temperature range. The memory system may also include a temperature-dependent biasing circuit that is configured to reduce a biasing voltage to the plurality of memory cells when the temperature of the array is at or near an upper end of the operating temperature range and increase the biasing voltage to the plurality of memory cells when the temperature of the array is at or near a lower end of the operating temperature range.


Find Patent Forward Citations

Bayat, Farnood. (2021). Temperature effect compensation in memory arrays (U.S. Patent No. 11170838). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11170838

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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