The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Apr. 24, 2020
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Min Sik Han, Icheon-si, KR;

Sung Chun Jang, Seoul, KR;

Jin Il Chung, Namyangju-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 7/10 (2006.01); H04L 7/00 (2006.01); H03L 7/081 (2006.01); G11C 29/56 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/1036 (2013.01); G11C 7/1051 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 11/4076 (2013.01); G11C 29/56012 (2013.01); H03L 7/0814 (2013.01); H04L 7/0037 (2013.01);
Abstract

A semiconductor device includes an internal clock generation circuit and a data processing circuit. The internal clock generation circuit delays first to fourth division clock signals, which are generated by dividing a frequency of a clock signal, by a delay time adjusted based on a first code signal and a second code signal to generate first to fourth internal clock signals. The data processing circuit aligns internal data in synchronization with the first to fourth internal clock signals to generate output data. The data processing circuit also interrupts generation of the output data based on first and second command blocking signals according to a point in time when a read command is inputted.


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