The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2021
Filed:
Jan. 07, 2020
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Sunil Gupta, San Diego, CA (US);
Scott Powers, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); H05K 1/18 (2006.01); H05K 1/02 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 3/0613 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01); H05K 1/0242 (2013.01); H05K 1/18 (2013.01); H05K 2201/09218 (2013.01); H05K 2201/10159 (2013.01);
Abstract
A wireline communications system is described. The wireline communications system includes a printed circuit board (PCB). The wireline communications system also includes a system on chip (SoC) die on the PCB. The wireline communications system further includes an external memory device coupled to a memory interface of the SoC die. The external memory device is coupled to the memory interface of the SoC die through a PCB trace. A length of the PCB trace is configured according to an operating speed of the memory interface.