The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2021
Filed:
Feb. 05, 2021
Xilinx, Inc., San Jose, CA (US);
Sarosh Azad, Fremont, CA (US);
Akshay Shetty, San Jose, CA (US);
Alex Warshofsky, Miami Beach, FL (US);
XILINX, INC., San Jose, CA (US);
Abstract
Embodiments herein describe a hardware solution where a reset monitor in an integrated circuit detects and reports unintentional resets. A glitch in a reset path can cause a logic block to initiate an undesired or unintentional reset. As a result, the local circuitry in the logic block resets which causes them to lose data and their current state. In the embodiments herein, the reset monitor can monitor the reset signals generated within the logic blocks in the circuit. The reset monitor can compare these reset signals to golden copies of the resets signals generated by the reset generator. If a reset signal generated within a logic block does not match the corresponding golden copy of the reset signal, the reset monitor determines that an unintentional reset has occurred.