The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Dec. 20, 2019
Applicant:

Kalray, Montbonnot Saint Martin, FR;

Inventors:

Benoit Dupont de Dinechin, Grenoble, FR;

Julien Le Maire, La Tronche, FR;

Nicolas Brunie, Grenoble, FR;

Assignee:

Kalray, Montbonnot Saint Martin, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30145 (2013.01); G06F 9/30101 (2013.01); G06F 9/485 (2013.01); G06F 9/544 (2013.01); G06F 17/16 (2013.01);
Abstract

The disclosure relates to a processor including an N-bit data bus configured to access a memory; a central processing unit CPU connected to the data bus; a coprocessor coupled to the CPU, including a register file with N-bit registers; an instruction processing unit in the CPU, configured to, in response to a load-scatter machine instruction received by the CPU, read accessing a memory address and delegating to the coprocessor the processing of the corresponding N-bit word presented on the data bus; and a register control unit in the coprocessor, configured by the CPU in response to the load-scatter instruction, to divide the word presented on the data bus into K segments and writing the K segments at the same position in K respective registers, the position and the registers being designated by the load-scatter instruction.


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