The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Sep. 25, 2018
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Alon Marcu, Tel-Mond, IL;

Judah Gamliel Hahn, Ofra, IL;

Shay Benisty, Beer Sheva, IL;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/10 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0631 (2013.01); G06F 12/10 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/657 (2013.01);
Abstract

The disclosure relates in some aspects to a controller of a data storage device, such as the controller of a solid state device (SSD) having non-volatile memory (NVM). In some aspects, the controller operates to prevent or reduce page faults in the host device. In one example, an outer mapping table of a set of page tables of a host device stores pointers to an inner mapping table in the SSD controller. The pointers are provided within memory access requests sent from the host to the SSD. The inner table maps the pointers to physical addresses in the SSD. The SSD detects page faults by identifying pointers that do not have corresponding entries in the inner table. The SSD allocates physical addresses to accommodate such access requests, then executes the requests on behalf of the host device. In this manner, the page fault is transparent to the host.


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