The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Oct. 31, 2018
Applicant:

National Technology & Engineering Solutions of Sandia, Llc, Albuquerque, NM (US);

Inventors:

Philip Gach, Kensington, CA (US);

Manasi Raje, Emeryville, CA (US);

Anup Singh, Danville, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B01L 3/00 (2006.01);
U.S. Cl.
CPC ...
B01L 3/502784 (2013.01); B01L 3/50273 (2013.01); B01L 3/502792 (2013.01); B01L 3/502707 (2013.01); B01L 3/502715 (2013.01); B01L 2200/0673 (2013.01); B01L 2300/0645 (2013.01); B01L 2300/0816 (2013.01); B01L 2300/0887 (2013.01); B01L 2300/165 (2013.01); B01L 2400/0427 (2013.01); B81B 2201/05 (2013.01); B81B 2203/04 (2013.01);
Abstract

The present disclosure relates to digital microfluidic systems. Particularly, aspects are directed to a digital microfluidic system that includes a droplet chip having a substrate, a plurality of electrodes and corresponding plurality of conducting vias or embedded conductive posts formed in the substrate, and a dielectric layer formed over the plurality of electrodes; and a control chip having a substrate, a plurality of transistors and corresponding wiring layers formed in the substrate, and a plurality of contacts formed over the plurality of transistors. Each of the plurality of contacts is electrically connected to a corresponding transistor of the plurality of transistors, and one or more of the plurality of contacts is removably connected to one or more of the plurality of conducting vias or embedded conductive posts such that one or more of the plurality of transistors are electrically connected to one or more of the plurality of electrodes.


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