The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Dec. 19, 2017
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Steven L. Pope, Cambridge, GB;

Dmitri Kitariev, Costa Mesa, CA (US);

Derek Roberts, Cambridge, GB;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/861 (2013.01); H04L 29/06 (2006.01); H04L 12/707 (2013.01); H04L 12/801 (2013.01); G06N 20/00 (2019.01); G06F 9/50 (2006.01); G06F 30/394 (2020.01);
U.S. Cl.
CPC ...
H04L 49/9068 (2013.01); G06F 9/5044 (2013.01); G06N 20/00 (2019.01); H04L 45/22 (2013.01); H04L 47/34 (2013.01); H04L 63/1416 (2013.01); H04L 63/1458 (2013.01); G06F 2209/509 (2013.01);
Abstract

A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.


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