The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Jun. 05, 2020
Applicant:

Inphi Corporation, Santa Clara, CA (US);

Inventors:

Radhakrishnan L. Nagarajan, Santa Clara, CA (US);

Liang Ding, Singapore, SG;

Mark Patterson, Santa Clara, CA (US);

Roberto Coccioli, Santa Clara, CA (US);

Steve Aboagye, Santa Clara, CA (US);

Assignee:

MARVELL ASIA PTE, LTD., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/80 (2013.01); H04B 10/40 (2013.01); H04J 14/02 (2006.01); H01L 23/538 (2006.01); H04B 10/50 (2013.01);
U.S. Cl.
CPC ...
H04B 10/801 (2013.01); H01L 23/5384 (2013.01); H04B 10/40 (2013.01); H04B 10/503 (2013.01); H04J 14/0278 (2013.01);
Abstract

A method for co-packaging multiple light engines in a switch module is provided. The method includes providing a module substrate with a minimum lateral dimension no greater than 110 mm. The module substrate is configured with a first mounting site at a center region and a plurality of second mounting sites distributed densely along the peripheral sides. The method includes disposing a main die with a switch processor chip at the first mounting site. The switch processor chip is configured to operate with a digital-signal processing (DSP) interface for extra-short-reach data interconnect. The method further includes mounting a plurality of chiplet dies respectively into the plurality of second mounting sites. Each chiplet die is configured to be a packaged light engine with a minimum lateral dimension to allow a maximum number of chiplet dies with <50 mm from the main die for extra-short-reach data interconnect.


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