The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Mar. 13, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Junghwa Kim, Seoul, KR;

Heeseok Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01Q 1/38 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/16 (2006.01); H01L 23/66 (2006.01); H01Q 9/04 (2006.01); H01Q 9/16 (2006.01);
U.S. Cl.
CPC ...
H01Q 1/38 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/66 (2013.01); H01L 24/05 (2013.01); H01L 24/24 (2013.01); H01L 25/16 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/24195 (2013.01); H01L 2224/24225 (2013.01); H01L 2924/19105 (2013.01); H01Q 9/0407 (2013.01); H01Q 9/16 (2013.01);
Abstract

An antenna module includes an antenna substrate, a fan-out package and first electrical connection structures. The antenna substrate includes a pattern layer including antenna and ground patterns, and a feeding layer under the pattern layer including a feeding network that supplies power to the antenna patterns. The fan-out package is under the antenna substrate and includes a semiconductor chip driving the antenna substrate, an encapsulant encapsulating some of the semiconductor chip, a first redistribution layer on the semiconductor chip electrically connecting the semiconductor chip with the antenna substrate, and a second redistribution layer under the semiconductor chip electrically connecting the semiconductor chip with external devices. The first electrical connection structures are between and electrically connect the antenna substrate and the fan-out package. A logic layer including logic patterns electrically connecting the pattern layer with the feeding layer in the antenna substrate in the first redistribution layer in the fan-out package.


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