The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Jul. 01, 2019
Applicant:

Newport Fab, Llc, Newport Beach, CA (US);

Inventor:

Paul D. Hurwitz, Irvine, CA (US);

Assignee:

Newport Fab, LLC, Newport Beach, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/12 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/76243 (2013.01); H01L 21/76289 (2013.01); H01L 29/0649 (2013.01);
Abstract

A semiconductor-on-insulator (SOI) device including a handle wafer, a buried oxide (BOX), and a top device layer is provided. A plurality of elongated trenches are formed in the handle wafer. Air gaps are formed in the elongated trenches by pinching off each of the elongated trenches. In one approach, prior to the pinching off, a plurality of lateral openings are formed contiguous with the elongated trenches and adjacent to the BOX. The elongated trenches and/or the lateral openings reduce parasitic capacitance between the handle wafer and the top device layer. In another approach, sidewalls of the elongated trenches are implant-damaged so as to further reduce the parasitic capacitance between the handle wafer and the top device layer.


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