The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Jan. 02, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jung-ho Do, Hwaseong-si, KR;

Sang-hoon Baek, Seoul, KR;

Tae-joong Song, Seongnam-si, KR;

Jong-hoon Jung, Seongnam-si, KR;

Seung-young Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 23/528 (2006.01); H01L 29/78 (2006.01); H01L 27/07 (2006.01); H01L 27/02 (2006.01); H01L 29/417 (2006.01); H01L 23/522 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/0207 (2013.01); H01L 27/0705 (2013.01); H01L 27/092 (2013.01); H01L 29/41741 (2013.01); H01L 29/7827 (2013.01); H01L 21/823487 (2013.01); H01L 21/823885 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01);
Abstract

An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.


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