The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Jan. 14, 2020
Applicant:

Qromis, Inc., Santa Clara, CA (US);

Inventors:

Vladimir Odnoblyudov, Danville, CA (US);

Dilip Risbud, San Jose, CA (US);

Ozgur Aktas, Pleasanton, CA (US);

Cem Basceri, Los Gatos, CA (US);

Assignee:

QROMIS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 33/00 (2010.01); H01L 21/762 (2006.01); H01L 21/311 (2006.01); H01L 33/02 (2010.01);
U.S. Cl.
CPC ...
H01L 21/02505 (2013.01); H01L 21/0245 (2013.01); H01L 21/0254 (2013.01); H01L 21/02389 (2013.01); H01L 21/02488 (2013.01); H01L 21/02513 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 21/0242 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 21/02658 (2013.01); H01L 21/31111 (2013.01); H01L 21/76254 (2013.01); H01L 33/007 (2013.01); H01L 33/02 (2013.01);
Abstract

A method of forming a plurality of devices on an engineered substrate structure includes forming an engineered substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesion shell, encapsulating the first adhesion shell with a barrier layer, forming a bonding layer on the barrier layer, and forming a substantially single crystal layer coupled to the bonding layer. The method further comprises forming a buffer layer coupled to the substantially single crystal layer, forming one or more epitaxial III-V layers on the buffer layer according to requirements associated with the plurality of devices, and forming the plurality of devices on the substrate by removing a portion of the one or more epitaxial III-V layers disposed between the plurality of devices and removing a portion of the buffer layer disposed between the plurality of devices.


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