The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 2021
Filed:
Sep. 05, 2019
Applicant:
Toshiba Memory Corporation, Tokyo, JP;
Inventors:
Hiromi Noro, Kanagawa, JP;
Yusuke Ochi, Kanagawa, JP;
Takahiro Sugimoto, Kanagawa, JP;
Naoaki Kanagawa, Kanagawa, JP;
Assignee:
TOSHIBA MEMORY CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01); G11C 16/32 (2006.01); G11C 16/10 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 5/063 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/32 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01);
Abstract
According to one embodiment, a semiconductor memory device includes: a memory cell array; a conversion circuit; a data bus; a first buffer and a second buffer; and a third buffer. The data bus includes a first wiring part extending along a first direction. The first buffer and the second buffer are separate from each other. The first to third buffers are at different positions along the first direction.