The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

May. 17, 2019
Applicant:

Emc Ip Holding Company Llc, Hopkinton, MA (US);

Inventors:

Junping Zhao, Beijing, CN;

Jinpeng Liu, Shanghai, CN;

Kun Wang, Beijing, CN;

Assignee:

EMC IP Holding Company LLC, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06N 20/00 (2019.01); G06F 16/245 (2019.01); G06F 16/22 (2019.01);
U.S. Cl.
CPC ...
G06F 9/5044 (2013.01); G06F 9/4881 (2013.01); G06F 9/5083 (2013.01); G06F 16/22 (2019.01); G06F 16/245 (2019.01); G06N 20/00 (2019.01);
Abstract

A method comprises obtaining hardware information of a plurality of dedicated processing resources, wherein the plurality of dedicated processing resources comprises a first dedicated processing resource and a second dedicated processing resource, and the hardware information comprises first hardware information of the first dedicated processing resource and second hardware information of the second dedicated processing resource. The method further comprises generating a first task based on the first hardware information and a second task based on the second hardware information, and allocating the first task to the first dedicated processing resource and the second task to the second dedicated processing resource. For task scheduling in heterogeneous dedicated processing resources (for example, accelerator devices) scenario, the method generates corresponding kernel codes according to different hardware capabilities. Thus, dynamic optimization for the heterogeneous dedicated processing resources is implemented, thereby improving resource utilization rate and execution efficiency.


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