The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Jul. 29, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Brian D. Barrick, Pflugerville, TX (US);

Sundeep Chadha, Austin, TX (US);

Sheldon Bernard Levenstein, Austin, TX (US);

Phillip G. Williams, Cape Coral, FL (US);

Niels Fricke, Herrenberg, DE;

Dung Q. Nguyen, Austin, TX (US);

Brian W. Thompto, Austin, TX (US);

Christian Gerhard Zoellin, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30181 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01);
Abstract

Technology for fusing an add-immediate instruction with a load-immediate instruction (or store-immediate instruction) in a microprocessor. This can result in quicker address generation while performing a load and store operation.


Find Patent Forward Citations

Barrick, Brian. (2021). Fusion to enhance early address generation of load instructions in a microprocessor (U.S. Patent No. 11163571). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11163571

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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